An Efficient Design of 8-bit High Speed Parallel Prefix Adder

 

Garima Thakur, Harsh Sohal, Shruti Jain

Department of Electronics and Communication Engineering, Jaypee University of Information Technology, Solan

 

Abstract:

This paper discusses the comparison of various addition algorithms for different performance parameters like speed, area and power. We have studied and implemented different adders like ripple carry adder, carry skip adder, carry select adder, carry look ahead adder, Kogge stone adder and carry increment adder. To get great performance in processing system or in other multi-core devices, adders are always termed to be the most basic requirements. If the speed of adder improves or fastens, then there will be an automatic improvement in the speed of the system. Verilog coding is used for comparative analysis of various adders. Using Xilinx ISE 14.1 Design Suite various adders are simulated and synthesized for Spartan 3E FPGA. 4-bit Kogge stone adder was found to have less delay (8.608ns) and low power (0.042 W) than other 4-bit adders. The proposed 8-bit Carry increment adder using Kogge stone adder was implemented which has basic significant reduction in delay with 12.345ns and power with 0.054 W.

 

 

1. INTRODUCTION:

In digital system an adder circuit plays an important role and is the most basic block. When we use digital system on a VLSI chip, much better signal processing systems are implemented with the growth in the scale of integration. A large amount of energy and computation capacity is consumed in the signal processing. A critical hardware unit is formed from the unit adders, which helps in the well organized implementation of an arithmetic operation. Half Adder (HA) and Full Adder (FA) are the basic building blocks. Using these basic building blocks all complicated adders architectures are implemented. Those complicated adders are Carry skip adder(CSkA), Carry select adder(CSLA),Carry look ahead adder(CLA),Ripple carry adder(RCA),Kogge stone adder(KSA) which are discussed as follows:

 

a)      Ripple Carry Adder (RCA):

Multi-bit addition is performed by the RCA and moreover the processing delay is also increased by it. RCA is formed by cascading full adders in series [1-3]. Each full adder generates a carry which is provided to next full adder and the process goes on, which is shown in Fig 1. The delay is increased, when the numbers of bits go on increasing. The advantage of RCA is its easy implementation and simple design [4].

Fig 1: 4 bit Ripple carry adder

b)      Carry Select Adder (CSLA):

CSLA is formed by two RCA and 2:1 multiplexer. Independent generation of sum and carry i.e. c_in=1 and c_in=0 are executed parallelly in Carry select adder. Correct sum along with correct carry-out is then selected by the multiplexer, depending on real carry-out of previous section. CSLA is further divided into two blocks i.e. uniform and variable block. More hardware is used by CSLA even though it gives less delay compared the ripple carry adder [2]. Schematic design of 4- bit CSLA is shown in Figure 2.

 

Fig 2: 4-bit Carry select adder

 

c)      Carry Skip Adder (CSkA):-

This adder enhances delay of RCA with small effort. As the name indicates, CSkA uses skip logic in the propagation of carry. It is designed to speed up a wide adder by adding the propagation of carry bit around a portion of the entire adder. The carry-in bit designated as C_i. The output of RCA (the last stage) is C_i+4. The carry skip circuitry consists of two logic AND gate which accepts the carry-in bit and compares it with the group of propagated signals using the individual propagate values [1, 2, 5].

 

P _{[ i,i+3 ]} = (P _i+3 )*(P _i+2 )*(P _i+1 )*P _i                                            (1)

 

Output stage is produced when the output from the AND gate is ORed with C_out of RCA. Final carry is expressed by output stage which is represented by Equation 2.

 

Carry = C _i+4 +(P _i,i+3 ) * C _i                                          (2)

 

If P _{[ i,i+3 ]} = 0, then the Carry-out of the group is determined by the value of C_i+4 .However, if  P _{[ i,i+3 ]} =1 then the Carry-in bit is C_i =1,then the group carry-in is automatically sent to the next group of adders. The design of schematic of CSkA is shown in Figure 3.

 

 

Fig 3: 4-bit Carry skip adder

 

d)      Carry Look Ahead Adder (CLA):

The RCA is simple and easy to implement, but it suffers from serious delay issues. This is because the next stage of full adder needs to wait for Carry bit from the previous stage full adder The CLA solves this problem by calculating the carry signals in advance, based on the input signals [6, 7, 8].CLA technique is to drive the 'Sum' and 'Carry' outputs by using intermediate terms defined as ‘Generate (G)' and ‘Propagate (P)' terms. In the case of propagate the 'Carry-out' depends on the 'Carry-in' and in the case of generate the ‘Carry-out’ independent of the ‘Carry-in’.

 

Table 1: Truth Table of a Full Adder

 

The Table 1 illustrates the concept of Propagate and Generate more clearly. The output 'Sum' and 'Carry' of the full adder in terms of P and G, can be observed from Table 1 as expressed by eq. 3 and eq. 4:

S _i =P_i ⊕ C_i                                                                                      (3)

C _i+1 =G_i +(P_i .C_i )                                                                           (4)

 

Weinberger and Smith proposed a method for fast carry generation which states that the carry need not depend on the previous carry which is shown in Fig 4:

 

 

Fig 4: 4-bit Weinberger-Smith CLA

 

Generate term produces a carry-out independent of the carry-in, i.e.no matter what the carry-in, the carry-out is always '1', when both of the inputs A and B are '1' thus G=A.B. The Propagate term transfers the input Carry as output Carry when only one of the inputs is high.

 

The carry generation is done by first calculating Generate(g_i ) and Propagate (p_i ) which is explained by eq. 5 and eq. 6 respectively.

g_i =A_i.B _i                                                                            (5)

p_i =A_i ⊕ B_i                                                                        (6)

Carry is generated by eq. 7 as:

C_i =g _i-1 + p _i-1 C _i-1                                                           (7)

 

After the carries are generated, the sum is calculated using the eq. 8.

S_i =A_i ⊕ B_i ⊕ C_i                                                             (8)

 

For wide adders where N > 16 (N is the input operand size), the delay of the carry look-ahead adders becomes dominated by the delay of passing the carry through the look-ahead stages and the implementation need high fan-in gates.

e)      Kogge Stone Adder (KSA):

It is basically a prefix based adder [6, 9-11]. Prefix adder includes three stages i.e:  pre-computation stage, prefix network stage and post-computation stage which is shown in Fig 5.

Fig 5: Block level diagram of a prefix adder

 

1.      Pre-Computation:

It computes the carry 'Propagate' and carry 'Generate' bits for each input pair as given by eq. 9 and eq. 10 [9, 10].

 

Generate,G_i = A_i AND B_i                                                                (9)

Propagate,P_i = A_i XOR B_i                                                               (10)

 

 

Fig 6: 4-bit Kogge-Stone prefix adder

 

2.      Prefix Network:

It computes the final carry from the carry 'Propagate' and carry 'Generate' bits which is expressed by eq. 11 and eq. 12 [11].

 

Propagate, P = P_i AND P_iprev                                                        (11)

Generate,G = (P_i AND G_iprev ) OR G_i                                           (12)

 

3.      Post Computation: 

It computes the final Sum from carry generated in the prefix network stage. Final sum and final carry is expressed by eq. 13 and eq. 14 respectively.

 

Sum,S _i = P_i XOR C_i-1                                                                    (13)

Carry,C _i = G _i                                                                                (14)

 

The KSA is the parallel prefix form that takes more area to implement, but has a lower fan-out at each stage. KSA started being used in multi-bit addition for faster addition but wiring congestion is often a problem [15, 16].The KSA tree structure of 4 bit has been shown in Fig. 6.

 

Fig. 7 shows the colored representation of Fig. 6. This figure also explains the equations for calculating Propagate and generates terms.

Fig 7: Representation of each block

 

Later section of the paper is organized as: Section 2 provides a brief literature review of the related work on adders. Section 3, explains the simulation work done for implementation of 4-bit adders. In section 4, design of carry increment and modified carry increment adder was presented and finally conclusion and future work was explained.

 

2. LITERATURE REVIEW:

Gurjar P. et al. 2011[1] simulated and synthesized the different adders. The parameters like area and speed and the usefulness of fast adders is analyzed by simulated results. In the end, for 8-bit and 16-bit adders the caught parameters are analyzed. This paper infers that in terms of speed and area consumption the Carry skip adder is the efficient adder.

 

Bais K. et al 2016 [4] mentioned comparison of delay and area of various adders for different number of bits. From the delay comparison of adders, it is clear that KSA, a representative of parallel prefix adders, is the fastest. In the end they drive a conclusion that the speed and area cannot be optimized at the same time. If one parameter is improved the other definitely shows degradation. In this paper we understand that KSA was the best when considered for delay but for area, as the number of bits of operands increases KSA occupies more area due to increase in parallel prefix stage.

 

Nandini M. et al 2015[6] discussed different kinds of prefix adders particularly Spanning adder, Sparse Kogge stone adder, Ladner fischer adder, Brent Kung adder and Kogge Stone adder. Correct practicality of every individual module was tested. This paper has resulted in reduced delay and power in the development of adders design. After analysis designed Kogge stone adder and Sparse Kogge stone adders different parameters is being compared with the other adder. After the comparison less combinational delay of Kogge Stone adder with 12.499ns and less amount of power consumption of Ladner fischer adder with 0.26089 mW. In future using parallel prefix adders all the proposed architectures are designed.

 

Kulkarni R. et al 2015[12], discussed the performance of different adders. Characterization of different adders and implementation on an FPGA is done. After observing the results of comparisons, for two 8 bit numbers addition, CLA is better. For three and four 8 bit numbers addition Carry save adder with last stage built by RCA is preferable. In future work, low area as well as delay is required to design unique adder and to meet the requirement of current industry.

 

Mitre A. et al 2015[13], this paper compared completely different addition rule for various performance parameters i.e. power, area and speed for different adders such as Ripple carry adder, Carry save adder, Carry select adder, Carry look ahead adder and Kogge stone adder. By merging Kogge stone and Carry select algorithms a high speed adder is then designed and works significantly faster than the rest.

 

Kumar A. et al 2013[17] explained that Ripple carry adder design is basic and it is appropriate for just addition of less width operand since delay run straightly with the width of operand. Linear area required by Carry skip adder which is not really bigger than area required by the RCA. As compare to other the delay of CLA is less and much faster than RCA. For high speed multiplication and accumulation, they can use Carry-look ahead adder for 32 bit multiplier-accumulator unit. In fact the speed of multiplier has approximately twice the speed with carry-look ahead adder.

 

SaiKumar M. et al 2013[18], in this paper, performance parameters of adders such as delay and area are compared and determined and design of various adders are discussed. Better performance in terms of area and delay is achieved through Carry increment adder as compared to other adder topologies. For the later use, design of unique adder is needed which will provide low area as well as delay and meet the needs of current VLSI industry.

 

Suba C. et al 2014[19], design for reconfigurability (DFR) technique is presented by this paper for CLA.DFR scheme which has proposed to isolate an extensive CLA into different separate small ones.  A small amount of area and delay penalty is incurred by the DFR scheme. The CLA has the least delay-area product. It is suitable for situations where both low power and fastness application places. It is not possible to use CLA in constant delay for the wider-bit adders as there will be larger delay, larger power consumption and substantial loading capacitance.

 

3. IMPLEMENTATION OF 4-BIT ADDERS:

For implementation of 4-bit adders we have used Xilinx ISE 14.1 Design Suite, area and delay values are calculated from synthesis report while Power is calculated by Power analyzer in which we calculated IOs Power and Leakage Power. The terms used in Table 2 are explained as follows [12-14]:

 

a)      Look-Up Tables (LUT):-

In Configurable Logic Block (CLBs) function generators are implemented using LUT. When LUT’s inputs are given then a block of SRAM is indexed. The output of LUT depends on whatever value is in indexed location in its SRAM. This is because when chip is powered up, contents have to initialise and as RAM is volatile.

 

b)      Slices: -

In FPGA slices are the basic building block components. Before mapping the logic of design, number of elements which each slice contain make up. All of the Flip flop and LUT’s are packed into slices after mapping, not necessarily filling the slices. In the map report, even partially used slice is counted in the “occupied slices”.

 

c)      Input/Output Block (IOB):-

In FPGA device, input and output functions are implemented from the grouping of basic elements. Such collection and grouping of basic elements is termed as an IOB.

 

d)      Delay: -

Delay is the time required for the input to be propagated to the output. In other words, the delay of a logic gate is defined as the time it takes for the effect of a change in input to be visible at the output

·        Router delay: - Router delay can be ~40% of total delay.

·        Logic delay: - Logic delay can be more than 50% of total delay.

 

e)      Power: - Power dissipation of two types a) static b) dynamic.

·        Static power dissipation- Static power lost is due to current leakage in the transistors of an FPGA.

·        Dynamic power dissipation- Dynamic power consumption is caused by signal alteration.

 

The comparison of different adders in terms of area, delay and power is shown in Table 2.

 

 

Table 2: Comparison of different adders

Sr. No.	Design	No. of 4 I/P LUT	No. of occupied slices	No. of bonded IOB		Delay (ns)		Power Total (W)		Power Delay Product
				I-Buf	O --Buf	Logic Delay	Router Delay	Power IOs	Power Leakage
1.	4 bit RCA	8	4	9	5	7.306	2.768	0.021	0.034	0.543
2.	4 bit Carry Skip adder	10	6	9	5	6.602	2.134	0.012	0.034	0.401
3.	4 bit Carry Select adder	11	6	9	5	6.637	2.099	0.021	0.034	0.471
4.	4 bit Carry look ahead adder	8	4	9	5	7.306	2.576	0.008	0.034	0.415
5.	4 bit Kogge stone adder	7	4	9	5	6.602	2.006	0.008	0.034	0.361

 

COMPARISON TABLE:

Table 3 gives the comparison of designed 4-bit RCA with the existing adder. Our proposed circuit gives the best delay i.e 10.074 ns in comparison with Bais K. et al 2016 whose delay is 12.008ns. We have also calculated Power which is 0.054W while Bais K. et al 2016 has not reported any power.

 

Table 3: Delay and Power calculation of 4-bit RCA

 

Table 4 gives the comparison of designed 4-bit KSA with the existing adder .Our proposed circuit gives the best delay i.e. 8.608 ns in comparison with Bais K. et al 2016 whose delay is 11.786 ns. We have also calculated Power which is 0.042W while Bais K. et al 2016 has not reported power.

 

Table 4: Delay and Power calculation of 4-bit KSA

 

Table 5 gives the comparison of designed 4-bit CLA with the existing adder. Our proposed circuit gives the best delay i.e. 9.882 ns in comparison with Bais K. et al 2016 whose delay is 12.008ns. We have also calculated Power which is 0.042Wwhile Bais K. et al 2016 has not reported power.

 

Table 5: Delay and Power calculation of 4-bit CLA

 

 

4. PROPOSED ADDERS:

Among the parallel adders Carry Increment Adder (CIA) has the best delay performance which is one of the most important parameter in the high speed devices [20-30]. The resulting CIA cuts the circuit size down by 23% with no change in performance. CIA is preferred for large word lengths (upto 128 bits) as the power delay product is smallest among all the known adder architectures. An 8-bit CIA adder includes two blocks of adder each 4 bit. In CIA only one partial sum is calculated and incremented if necessary, according to the input carry but in Carry select adder, from each group computing two partial sums and selecting the correct one. We have implemented modified 8-bit CIA using KSA which provides less delay then already implemented 8-bit CIA. As we have seen from Table 2, among all the 4-bit adders KSA has the best performance in terms of delay i.e. 8.608ns. Therefore, we have used KSA to implement 8-bit CIA.

 

a)     CIA using RCA:

CIA consists of incremental circuitry and RCA's. A desired number of 4-bit inputs adds by RCA and generating partitioned sum and partitioned carry. Using HA's in ripple carry chain with a sequential order the incremental circuit is designed. For example, two 4-bit RCA is required to implement an 8-bit CIA. From the first block of RCA, we directly get the 4-bit sum of CIA. And the first RCA block carry output is given as input to the C_in of an incremental circuit. The incremental circuit consists of half adders and the second RCA block the partial sum obtained is given to incremental circuit [9]. The block diagram of an 8-bit CIA_RCA is shown in Fig. 8.

 

 

Fig 8: Block diagram of CIA_RCA

 

b)     The KSA replaces the ripple carry adder, in order to reduce the delay of the regular CIA. The modified 8-bit CIA using KSA is shown in Fig. 9. KSA suffer from complexity in prefix network due to an increase in number of wiring and logic cells. A delay efficient KSA is proposed. Among the parallel adders carry increment adder has the best performance which is one of the most important parameter in the high speed devices. The proposed design is a new concept and to the best of our knowledge it has not been proposed earlier by any researcher.

 

CIA using KSA:

In this sub section, we present the modified Carry increment adder i.e. CIA_KSA. We know that RCA design is simple and implementation is easy, but it suffers from worst propagation delay. It is proved that KSA performs better than RCA in term delay at the expense of increased design complexity. We have modified CIA_RCA by replacing the RCA block with KSA block. Because of the property of KSA, the overall delay performance will be improved. As similar to CIA_RCA incremental circuit can be designed using HA's in ripple carry chain with a sequential order. The block diagram representation of CIA_KSA is shown in Fig. 9.

 

 

Fig 9: Block diagram of CIA_KSA

 

From the synthesis report, the performance parameters like area and delay are obtained and from power analyzer power is calculated which is shown in Table 6. It can be observed that the proposed design for 8bit Carry increment adder has better delay performance which is the desired goal of this research work.

 

Table 6: Area, Delay and Power calculation of 8 bit CIA

 

COMPARISON TABLE:

Table 7 signifies the comparison of designed 8-bit CIA with the existing adder. Our proposed circuit gives the best delay i.e. 12.345 ns for CIA_KSA in comparison with Devi A.B. et al 2016 [9] whose delay is 14.59 ns for CIA_RCA and 13.54 ns for CIA_CLA.

 

Table 7: Delay and Power calculation of 8-bit CIA using KSA

 

5. CONCLUSION:

The performance of any circuit in VLSI design limits by the constituent factors like power, delay and area. In this paper a modified carry increment adder is proposed using KSA instead of ripple carry adder. Without affecting the circuit the delay performance of the circuit is improved by replacing the 4-bit RCA with a proposed 4-bit KSA. But the proposed CIA_KSA has the disadvantage of more power consumption. The design is tested and verified by Verilog HDL coding and simulation is carried out by in Xilinx ISE 14.1 design suite and synthesized for Spartan 3E FPGA. The delay performance of KSA is better than RCA but as operand size increases (32-bits and above).  KSA suffers from complexity due to an increase in the number of logic cells and wiring. Future work may be dedicated to studying the complexity of CIA_KSA when the number of bits was increased.

 

6. REFERENCES:

1.       P. Gurjar, R. Solanki, P. Kansliwal & M. Vucha ,”VLSI Implementation of Adders for High Speed ALU”, International journal of Computer Applications, Vol. 29, No.10, September 2011.

2.       R. UMA, V. Vijayan, M. Mohanapriya & S. Pau, “Area, Delay and Power Comparison of Adder Topologies”, International Journal of VLSI design & Communication Systems (VLSICS), Vol.3, No. 1, February 2012.

3.       S. R. Sahoo & K. K. Mahapatra, “Design of Low Power and High Speed Ripple Carry Adder using Modified Feed through Logic”, Proceedings of IEEE International Conference on Communications, Devices and Intelligent Systems, West Bengal, pp.377-380, June 2012.

4.       K. Bais & Z. Ali, “Comparison of various adder designs in terms of delay and area”, International journal of science and research (IJSR), Vol. 5, Issue 5, May 2016.

5.       V. R. Hakki, “Design and Implementation of 4-bit Carry Skip Adder Using NMOS Pass Transistor Logic”, International Journal of Computer Science and Mobile Computing, Vol. 6, Issue 7, July- 2017, pp. 203-207.

6.       M. Nandini & A. Jayavani, “High Speed and Power Optimized Parallel Prefix Modulo Adders using Verilog”, International Journal of Advanced Technology and Innovative Research, Vol. 07, Issue 01, January 2015, pp. 0216-0133.

7.       J. Kaur & P. Kumar, “Analysis of 16 & 32 Bit Kogge Stone Adder Using Xilinx Tool”, Journal of Environmental Science, Computer Science and Engineering & Technology, Vol. 3. No. 3, June-August 2014.

8.       P. C. Kumari & R. Nagendra, “Design of 32 bit Parallel Prefix Adders”, IOSR Journal of Electronics and Communication Engineering (IOSR-JECE), Vol. 6, Issue 1, May - June 2013, pp. 01-06.

9.       D. H. K. Hoe, C. Martinez, & S. J. Vundavalli, “Design and Characterization of Parallel Prefix Adders using FPGAs”, 43rd Southeastern Symposium on System Theory, IEEE, pp. 168-172, 2011.

10.     K. Boddireddy, B. P. Kumar & C. S. Paidimarry, “Design and Implementation of Area and Delay Optimized Carry Tree Adders using FPGA”, International Conference on Computers and Communications Technologies, IEEE, pp. 1-6, Dec. 2014.

11.     S. K. Yezerla, & B. R. Naik, “Design and Estimation of delay, power and area for Parallel prefix adders”, IEEE Proceedings of 2014 RAECS, UIET, Panjab University, Chandigarh, pp. 1-6, March 2014.

12.     Kulkarni R. R., “Comparison among different adders”, IOSR journal of VLSI and Signal Processing (IOSR-JVSP), Vol. 5, Issue 6, Ver. 1 (Nov-Dec 2015), pp. 01-06.

13.     A. Mitra, A. Bakshi, B. Sharma & N. Didwania, “Design of a High Speed Adder”, International journal of Scientific and Engineering Research, Vol. 6, Issue 4, April 2015.

14.     S. Veeramachaneni, Design of Efficient VLSI Arithmetic Circuits, PHD thesis, International Institute of Information Technology, Hyderabad, June 2015.

15.     R. Thakur, S. Jain, M. Sood, “FPGA Implementation of Unsigned Multiplier Circuit Based on Quaternary Signed Digit Number System”, 4th IEEE International Conference on signal processing and control (ISPCC 2017), Jaypee University of Information technology, Waknaghat, Solan, H.P, India, pp.  637-641, September 21-23, 2017.

16.     R Thakur, S Jain, “ FPGA Implementation of Adder Circuit using Quaternary Signed Digit Number System”, Proceedings of the 11th INDIACom: 4th 2017 International Conference on Computing for Sustainable Global Development, BVICAM, New Delhi, March 1st  - 3rd, 2017, pp 6273-6277.

17.     A. Kumar & D. Sharma, “Performance Analysis of Different types of Adders for High Speed 32 bit Multiply and Accumulate Unit”, International journal of Engineering Research and Applications(IJERA),Vol. 3, Issue 4, Jul-Aug 2013, pp.1460-1462.

18.     M. Saikumar & P. Samumdiswary, “Design and performance analysis of various adders using verilog”, International journal of computer science and mobile computing, Vol. 2, Issue 9, September 2013, pp. 128-138.

19.     C. Suba, S. Karthick & M. Prakash, “Analysis of different bit Carry look ahead adder with reconfigurability in low power VLSI using Verilog code”, International journal of innovative research in computer and communication engineering, Vol. 2, Issue11, November 2014.

20.     A. B. Devi, M. Kumar & R. Laishram, “Design and Implementation of an Improved Carry Increment Adder”, International journal of VLSI design and Communication Systems (VLSICS), Vol.7, No. 1, February 2016 Conference on Computing for Sustainable Global Development, BVICAM, New Delhi.

21.     J. Shrivastava & G.S. Verma, “Retinex Theory for Image Enhancement”, Research Journal of Science and Technology, Vol. 2, Issue 6, 2010.

22.     P. K. Parikh, J. P. Soni, R. N. Patel, U. Y. Patel, K. N. Modi, H. M. Marvaniya & D. J. Sen, “Plagiarism: A Serious Malpractice in Latest Infrastructure through Webhunting”, Research Journal of Science and Technology, Vol. 2, Issue 6, 2010.

23.     K. Subbarayan, R. Kalyanaraman & S. Vijayanand, “Low-Cost Alternatives for Accelerating the Plant Cell Suspension Culture of Momordica charantia L.”, Research Journal of Science and Technology, Vol. 2, Issue 3, 2010.

24.     Mahalakshmi. R & Saranya. R, “Comparison of Software Requirements Tools”, Research Journal of Science and Technology, Vol. 9, Issue 2, April-June 2017.

25.     S. D. Kakde & S. S. Mane, “Lossless Data Compression Using Golumb Codes”, Research Journal of Science and Technology, Vol. 7, Issue 4, October-December 2015.

26.     S. Malagi, “Infringement of Copyright in Cyberspace: A Critical Study”, Research Journal of Science and Technology, Vol. 7, Issue 1, January-March 2015.

27.     S. R. Pattan, N. S. Dighe, D. S. Musmade, M. S. Kedar, S. K. Parjane, P. P. Gadhave  & M. S. Sanap, “Tools for Synthesis of Natural Products: An Overview”, Research Journal of Science and Technology, Vol. 1, Issue 2, 2009.

28.     S. S. Rajmane, S. R. Mathpati & J. K. Dawle, “Social Networking Applications for Schools and Colleges”, Research Journal of Science and Technology, Vol. 8, Issue 4, October-December 2016.

29.     C. A. Patel, D. J. Sen & A. R. Patel, “Nanomedicine: Emerging Field in Medicine”, Research Journal of Science and Technology, Vol. 2, Issue 3, 2010.

30.     R. W. Gaikwad & A. R. Warade, “Computer Aided Design of Multi-Component Distillation Column”, Research Journal of Science and Technology, Vol. 1, Issue 2, 2009.

 

 

Received on 13.11.2017       Modified on 20.01.2018 Accepted on 10.02.2018      ©A&V Publications All right reserved Research J. Science and Tech. 2018; 10(2):105-114. DOI: 10.5958/2349-2988.2018.00015.3